Search Search Hold time is the time for which data should be stable after the triggering edge of the clock to get latched properly by the flop. It may be negtive, zero and positive according to the path environment, but only positive or zero hold time is acceptable in FPGA. Jump to solution . That is to say, if a flip-flop defines a 200 ps data setup time,then the data must arrive 200 ps … To get the path met, either data path delay should be increased, or clock skew/hold requirement of capturing flop should be decreased. What is negative hold time and what does it specify physically? A negative hold slack means the path is violating hold timing check by the amount represented by hold slack.
Both setup and hold time for a flip-flop is specified in the library. Assume the flop which foundry gives us as a library part that has ports named as CLK-port, Data-port. First, that thread did not say that setup times should be specified as negative, it said that the particular setup time of the CLB flip flop is negative; the flip-flop will capture data as long as it arrives no later than 30ps or so after the clock, and remains valid for some amount of time after that (corresponding to the hold time). Thanks in advance rgds, prav.

Hold time refers a minimum time relative to the active clock edge that an input signal must be held at its valid setup logic level for guaranteed operation of the circuit. Figure 4: Positive level-sensitive D-latch. This window has an early edge > (commonly called set-up time, often specified as a min, but I would call > it a max), and it has a late edge (commonly called positive hold time > when it is later than the clock edge, negative hold time when it is > before the clock edge. negative hold time means input of the flop can change before the clock edge, and the old value will still be recognized I am confused though by this section of the link when describing negative setup time: Now imagine that you added a 2 ns delay line between the clock pin … It may be negtive, zero and positive according to the path environment, but only positive or zero hold time is acceptable in FPGA. Negative Setup Time and Negative Hold Time Concept Setup time is the minimum amount of time data must be stable at input before arriving the active edge of the clock. Significance of set_output_delay -max/-min negative and positive values? Depending upon the times of arrival of clock and data, hold time can be positive or negative. On 10 Feb 2004 01:32:42 -0800, [email protected] (prav) wrote: >What is negative hold time and what does it specify physically? For Setup Time >If the difference between the clock path and the data path …

Hold time refers to the time data can be hold effective after the clock edge. Now, in essence this is wrapper and should be treated as one.
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